In second-order Sigma-Delta analog/digital converters, briefly .SIGMA..DELTA. A/D, the analog circuit part is essentially based upon a circuit composed of two integrators (because of the second-order) of the switched-capacitor (SC) type connected in cascade. The output of the last integrator drives the input of a comparator that realizes, through a one-bit (in the majority of cases) D/A converter, a feedback which has repercussions on the same SC integrators. Accordingly, these SC integrators process the difference between the input signal and the feedback signal originating from the D/A feedback.
As in all SC circuits a double-sampled structure may be used to reduce current consumption. This structure is commonly referred to as a Lossless Discrete Integrator (LDI), and it is realized by simply duplicating each switched-capacitor structure and employing complementary control phases of the switches. In this way it is possible to attain the same function while halving the clock frequency that drives the switches. As a consequence, the current in the operational amplifiers can be reduced considerably because the time available for the settling of the amplifiers themselves is doubled. This general concept is illustrated in FIG. 1.
FIG. 2 shows a classical second-order single-sampled .SIGMA..DELTA. modulator. The purpose of this circuit is to assure, in the baseband of the signal to be converted, a satisfactory signal-to-noise ratio. This is done by "shifting" the quantization noise of the converter into a high frequency range. The consequent digital part of the .SIGMA..DELTA. converter will eliminate the high frequency noise by a digital filtering, supplying the data corresponding to the input signal with a resolution (number of bits of the data output by the A/D converter) defined by the signal-to-noise ratio of the same circuit. The resolution of these A/D converters is determined by the ratio between the clock frequency of the SC circuits and the band of the signal to be converted as disclosed, for example, in J. C. Candy: A use of double integration in sigma delta modulation, IEEE Transaction on Communications, Vol. COM-33, No. 3, pp. 249-258, March 1985.
The problem of realizing a second-order .SIGMA..DELTA. modulator using double-sampled SC integrators has been approached in different manners. The most serious problem of a double-sampled approach is represented by the aliasing of the high frequency quantization noise in the baseband (the band of interest) caused by mismatches among the switched-capacitors that realize the double-sampled structure as disclosed, for example, in P. J. Hurst. W. J. McIntyre: Double sampling in switched capacitor delta-sigma A/D converters, in ISCAS proc., pp. 902-905, New Orleans, May 1990. This aliasing considerably degrades the signal-to-noise ratio (SNR) of the A/D converter to the point of making not viable the use of a double-sampled structure for the realization of a second-order .SIGMA..DELTA. modulator.
To overcome this problem, a first approach, as disclosed, for example, in T. V. Burmas, K. D. Dyer, P. J. Hurst and S. H. Lewis: A second-order double-sampled delta-sigma modulator using additive-error switching, IEEE Journal of Solid State Circuits, Vol. SC-31, pp. 284-293, March 1996, which uses a sequential logic which, by considering the "history" of the output signal of the circuit, succeeds in eliminating the aliasing caused by the double-sampled structure. This is done by acting on the switches that realize the feedback in the SC integrators (.SIGMA..DELTA. Modulator with additive-error switching).
However, this known circuit is very complex as it increases considerably both the number of switches and of the needed control signals, as well as the number of switched-capacitors. It has a resulting increase in the area occupied and with the further disadvantage of rendering practically impossible a low supply voltage realization because of the many control signals for the switches that need to be boosted.
A second known approach is disclosed, for example, in D. Senderowicz, G. Nicollini, S. Pernici, A. Nagari, P. Confalonieri and C. Dallavalle: Low-voltage double-sampled .SIGMA..DELTA. converters, in ISSCC Dig. of Tech. paper, pp. 210-211. Febuaray 1997. This approach eliminates the aliasing of the high frequency quantization noise by realizing a fully floating structure that converts an eventual switched-capacitor mismatch into a common mode signal (Bilinear .SIGMA..DELTA. Modulator).
The main limitation of this known structure is that of requiring the realization of bilinear SC integrators. Moreover, these bilinear SC integrators increase considerably the internal gains of the circuit, with a consequent reduction of the dynamic range of the SC integrators and a degrading of the signal-to-noise ratio (SNR) by about 6 dB.